Random access to decompressed blocks

ABSTRACT

A system comprises a data storage, a decompression accelerator configured to decompress compressed data and thereby generate decompressed data, and a direct memory access (DMA) engine coupled to the data storage and the decompression accelerator. The DMA engine comprises a buffer for storage of a plurality of descriptors containing configuration parameters for a block of compressed data to be retrieved from the data storage and decompressed by the decompression accelerator, wherein at least one of the descriptors comprises a threshold value. The DMA engine, in accordance with one or more of the descriptors, is configured to read compressed data from data storage and transmit the threshold value and the compressed data to the decompression accelerator. The decompression accelerator is configured to decompress the compressed data until the threshold value is reached and then to abort further data decompression and to assert a stop transaction signal to the DMA engine.

BACKGROUND

Electronic data storage needs are growing, thereby calling upon furtherinvestments in electronic storages and hence increased costs. Oneapproach to cutting data storage costs is to compress data prior tostorage so that more data can be stored in less storage space. Forexample, if 100 MB of uncompressed data is compressed to 10 MB ofcompressed data, the amount of data storage needed is significantlyreduced, thereby reducing costs. To read the compressed data, the datamust first be decompressed.

Some kinds of data are highly structured, such as databases. To read aparticular record from within a database that is stored in compressedform, the system may decompress the entire database or an entire blockof the database to access the particular record in decompressed form.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of various examples, reference will now bemade to the accompanying drawings in which:

FIG. 1 shows a system in accordance with various examples;

FIG. 2 shows a descriptor data structure in accordance with variousexamples;

FIG. 3A shows a plurality of exemplary source descriptors associatedwith a data storage read transaction in accordance with variousexamples;

FIG. 3B shows a plurality of exemplary destination descriptorsassociated with a data storage read transaction in accordance withvarious examples;

FIG. 4 shows a direct memory access (DMA) engine in accordance withvarious examples;

FIG. 5 shows a compression/decompression accelerator in accordance withvarious examples; and

FIG. 6 shows a flow chart of a method in accordance with variousexamples.

DETAILED DESCRIPTION

Various embodiments of apparatus and methods are described herein thatprovide efficient access to storage in some computer systems. In aneffort to conserve storage resources, data may be compressed and storedin compressed form in a storage device (e.g., hard disk drive,solid-state storage drive, etc.). While storing data in compressed formreduces the need for higher capacity storage systems, the random accessof data within a structured compressed data set is problematic. Forexample, a database containing 50,000 records may be compressed andstored in compressed form. Because the database is compressed, retrievalof an individual record within the compressed database generallyrequires the decompression of the entire database.

The disclosed embodiments are directed to a direct memory access (DMA)engine in combination with a compression/decompression accelerator (alsotermed a compression/decompression engine) to obtain a selected portionof decompressed data from a block of compressed data. In response to aread request from a central processing unit (CPU), the DMA engine readscompressed data from storage and provides the stream of compressed datato the compression/decompression accelerator for decompression of thedata. The DMA engine also may provide a threshold value, supplied to itby the CPU, to the compression/decompression accelerator to indicatewhere data of interest is located relative to the decompressed block ofdata. When the compression/decompression accelerator decompresses theblock of data from its initial data values (e.g., bytes) to theindicated threshold in the decompressed data, thecompression/decompression accelerator may stop further processing ofcompressed data and may send a transaction stop signal to the DMAengine. In an embodiment, the DMA engine may further send a transactionidentity, such as a transaction number, to the compression/decompressionaccelerator on initiation of a data decompression transaction. In thiscase, the compression/decompression accelerator sends the transactionidentity with the transaction stop signal to the DMA engine.

When the DMA engine receives the transaction stop signal the DMA enginemay cease reading additional compressed data, thereby conserving theprocessing time and power the DMA engine otherwise would have consumedin reading the remainder of the compressed data block. Also, by stoppingthe reading of additional compressed data, bandwidth on the data bus(e.g., DRAM/PCIe bandwidth) that the DMA engine would otherwise consumemay be saved. The conserved processing time may be used to perform otherstorage access processing, thereby reducing the latency and increasingthe throughput of the storage system that may include the DMA engine.

FIG. 1 shows an example of a system 100 comprising an application 107executing in a virtual machine (VM) 105 on a server computer 102 thatwrites to and reads from a storage system 103 via a network 106. In anembodiment, the system 100 may be a computing environment supported by acomputing service provider. In some embodiments, the computingenvironment of system 100 comprises a provider network to which one ormore customers are subscribers. The customers of the provider networkcan access the provider network to request the creation of one or morevirtual machines to execute whatever applications 107 the customer sochooses. It is understood that the system 100 may comprise any number ofsevers 102, each server 102 can execute one or more virtual machines onbehalf of different customers, and each virtual machine may be used toexecute one or more applications 107. The network 106 may be a privatenetwork comprising switches, routers, etc., within the provider networkto communicatively couple together the servers 102, the storage system103, and any other devices and systems of the provider network.

The storage system 103 includes or otherwise has access to storage 104.The storage 104 may comprise non-volatile storage such as magneticstorage (e.g., hard disk drives), solid-state storage drives, or othertypes of mass storage devices. Storage 104 may comprise a single storagedevice or multiple storage devices. In addition to storage 104, thestorage system 103 comprises a processor 110, memory 112, a DMA engine114, and a compression/decompression accelerator 116. The access to thestorage 104 is mediated by the processor 110. The processor 110 mayreceive requests from, for example, application 107 to read and writedata from and to the storage 104. The processor 110 may delegate writingof data to and reading of data from the storage 104 to the direct memoryaccess (DMA) engine 114. In an embodiment, the storage system 103 may beimplemented as one or more server computers, where each server maycomprise one or more processor 110, one or more memories 112, one ormore DMA engines 114, and one or more compression/decompressionaccelerators 116.

For example, the processor 110 may receive from the application 107 awrite request with uncompressed data to be written to storage 104. Theprocessor 110 may store the uncompressed data received from theapplication 107 in the memory 112, or the data from the application 107may be stored in memory 112 by way of a separate interface that does notinclude the processor 110. The memory 112 of the storage system 103 maybe used as a temporary buffer in which pending read and write requestsfrom various customer applications 107 may be stored pending executionby the processor 110 with respect to storage 104.

Based on the read and/or write requests, the processor 110 generates amanifest or description defining the data transaction to be performed bythe DMA engine 114. The manifest may comprise a plurality of sourcedescriptors that identify locations or buffers in the memory 112 for theDMA engine 114 to read uncompressed data from and a plurality ofdestination descriptors that identify locations in the storage 104 forthe DMA engine 114 to write compressed data to. Each descriptor definesa contiguous span of memory 112 or storage 104.

For a write transaction in which uncompressed data from memory 112 is tobe compressed and written to storage in compressed form, the DMA engine114 reads the manifest, reads the uncompressed data beginning at thelocations or buffers in the memory 112 identified by the sourcedescriptors of the manifest, and sends the uncompressed data to thecompression/decompression accelerator 116 to be compressed. Thecompression/decompression accelerator 116 compresses the data providedby the DMA engine 114 and sends the compressed data back to the DMAengine. The DMA engine 114 writes the compressed data into the storage104 starting at locations or buffers defined by the destinationdescriptors. The DMA engine 114 may signal to the processor 110 that therequested write operation has completed, and the processor 110 maysignal to the application 107 that the requested write has beencompleted.

As another example, the processor 110 may receive a read request fromthe application 107. Based on the read request from the application, theprocessor 110 generates a manifest comprising a plurality of sourcedescriptors that identify locations or buffers in the storage 104 fromwhich the DMA engine 114 is to read compressed data and a plurality ofdestination descriptors that identify locations or buffers in the memory112 to which the DMA engine 114 is to write decompressed data pendingits return to the application 107. The DMA engine 114 reads themanifest, reads the compressed data starting at the locations or buffersin the storage 104 identified by the source descriptors, and sends thecompressed data to the compression/decompression accelerator 116. Thecompression/decompression accelerator 116 decompresses the compresseddata and returns decompressed data to the DMA engine 114. The DMA engine114 writes the decompressed data into locations or buffers in the memory112 identified by the destination descriptors. The processor 110 maythen read the decompressed data from the memory 112 and transmit thedecompressed data to the application 107, thereby completing the readrequest.

During a write operation, the DMA engine 114 may stream the uncompresseddata via, for example, a first Advanced eXtensible Interface (AXI)stream 118 to the compression/decompression accelerator 122. Thecompression/decompression accelerator 116 may compress the dataaccording to a compression algorithm that may be defined or selected bythe DMA engine 114 and may stream the compressed data back to the DMAengine 114 via a second AXI stream 120. AXI and AXI stream arespecifications defined by the advanced microcontroller bus architecture(AMBA), an open-standard, on-chip interconnect specification for theconnection and management of functional blocks in system-on-a-chip (SoC)designs.

During a read operation, the DMA engine 114 may stream the compresseddata via the first AXI stream 118 to the compression/decompressionaccelerator 122. The compression/decompression accelerator 116 maydecompress the data according to a decompression algorithm that may bedefined or selected by the DMA engine 114 and streams the decompresseddata back to the DMA engine 114 via the second AXI stream 120. While AXIstream interfaces are illustrated in FIG. 1, FIG. 4, and FIG. 5 anddiscussed in this specification, other interfaces and/or other interfacestandards may be used as well for communicating compressed,uncompressed, and decompressed data between the DMA engine 114 and thecompression/decompression accelerator 116.

When the processor 110 defines a span of compressed data to be read fromthe storage 104 by the DMA engine 114, it may be in response to arequest from the application 107 to read a specific location or sub-spanportion of that span of compressed data. For example, the application107 may submit a request to read a 13,000^(th) record in a specific file(e.g., record 13,000 in a database containing 50,000 records). Theprocessor 110 may map this file to a portion of storage 104 that extendsfrom the 1^(st) entry in the specific file to the 13,000^(th) record inthe specific file. The processor 110 may provide descriptors describingthe entire extents of the corresponding compressed data of the file inthe storage 104 because it does not know specifically where in thecompressed data the subject 13,000^(th) record may be located, becausecompression algorithms may be non-linear. The processor 110 may providethis location of the desired data relative to the location in thedecompressed file, data base, or blob in the form of the threshold tothe DMA engine 114 with the read request and descriptors. Alternatively,the processor 110 may provide the location or threshold in a separatecontrol word or in a metadata descriptor. Alternatively, the processor110 may provide the location or threshold to the DMA engine 114 bywriting into a register (not shown) of the DMA engine 114.

In an embodiment, when the DMA engine 114 receives a request from theprocessor 110 to read compressed data from the storage 104 (i.e.,receives a read manifest and/or descriptors identifying the readoperation and the location or locations in storage 104 to read from),the DMA engine 114 associates the read request with a storagetransaction, creates a transaction identifier for the storagetransaction, and sends the transaction identifier to thecompression/decompression accelerator 116. The transaction identifiermay be an integer that the DMA engine 114 generates in a sequencestarting from an initial value (e.g., 0) and incrementing upon each readrequest to be processed (e.g., 0, 1, 2, 3, etc.). The transactionidentifier may reset once a terminal value is reached. In an embodiment,the DMA engine 114 may receive the transaction identifier from theprocessor 110 rather than itself creating the transaction identifier.

The DMA engine 114 may transmit the transaction identity in the firstAXI stream 118 or via a different interface to thecompression/decompression accelerator 116. The DMA engine 114 furthermay transmit a threshold value or location in the decompressed data.This threshold value may identify a specific location of interest in thedecompressed data or may indicate the end of the stream of decompresseddata that is of interest or desired by the processor 110. This thresholdvalue may mark a single record that is desired by the application 107,such as record in a database. This threshold value may mark the end of aseries of entries or the last block of data that is desired by theapplication 107. The DMA engine 114 may also transmit a commandindicating that a decompression operation is desired. The command mayfurther identify which of a plurality of decompression algorithms are tobe employed to decompress a compressed data stream. Alternatively, theDMA engine 114 may simply send an identity of a decompression algorithmto be employed which inherently denotes that a decompression operationis commanded.

In an embodiment, the DMA engine 114 and the compression/decompressionaccelerator 116 may be implemented on a single substrate (e.g., packagedas a single semiconductor chip). In another embodiment, however, the DMAengine 114 and the compression/decompression accelerator 116 may beimplemented on different substrates and provided as two differentsemiconductor chips. The compression/decompression accelerator 116 maybe implemented as a single dual-function component that both compressesand decompresses data in accordance with one or more compression anddecompression algorithms as specified by the DMA engine 114.Alternatively, the compression/decompression accelerator 116 may beimplemented with two separate single-function components: a firstcomponent or block that performs compression and a second component orblock that performs decompression. Because the accelerator 116 mayperform either or both of data compression and decompression, by way ofshorthand, the accelerator may be referred to herein as a compressionaccelerator or as a decompression accelerator.

In an embodiment, when the compression/decompression accelerator 116(or, in other words, the decompression accelerator) decompresses astream of compressed data up to the threshold defined by the DMA engine114, it stops further processing of the compressed data received on thefirst AXI stream 118 and sends a stop transaction signal 122 to the DMAengine 114. The stop transaction signal 122 may be a dedicated signal orcontrol line or the stop transaction signal 122 may be a message sent onanother communication channel between the compression/decompressionaccelerator 116. The compression/decompression accelerator 116 (thedecompression accelerator) may further transmit the transaction identityof the subject transaction on the stop transaction signal 122 to the DMAengine 114. In response to the receipt of the stop transaction signal122 from the compression/decompression accelerator 116 (from thedecompression accelerator), the DMA engine 114 discontinues furtherreading of compressed data from the storage 104. The DMA engine 114 mayinitiate a next storage transaction.

Turning now to FIG. 2, an illustrative descriptor 130 is shown. Thedescriptor 130 may comprise an address field 132, a length field 134, acommand identity or command name field 136, a threshold value orlocation identity field 138, a first bit field 140 and a last bit field142. Descriptors 130 may have fewer or more fields than that shown inFIG. 2 depending on implementation use. For example, descriptors 130 tobe used to designate sources of data for a decompression operation maycomprise the threshold field 138 while descriptors 130 to be used todesignate sources of data for a compression operation may not comprisethe threshold field 138. The address field 132 may identify a startingaddress of a block of memory and the length field 134 may identify howlarge the block of memory is, for example a byte count. A singledescriptor 130 designates a contiguous extent of memory. The startingaddress and length fields thus specify that the memory transaction is tobegin, for example, reading a contiguous block of data whose length isspecified in the length field and the initial data value is located atthe starting address. The command field 136 may identify whether a readoperation or a write operation is to be performed on the storage 104.The command field 136 may further indicate whether the data is to becompressed or decompressed and further may indicate which of a pluralityof compression or decompression algorithms are to be employed in theread or write operation.

A single read or write access transaction may include a plurality ofdescriptors 130, particularly if the data to be read or written is not asingle contiguous block of data or is a size that exceeds the maximumsize defined by the length field 134. For example, a plurality ofdescriptors 130 may be used because a descriptor may be restricted toidentifying a maximum extent of storage 104, for example a maximum of 1MB block of storage 104, and more than the maximum extent of storagethat may be identified by a single descriptor are the object of thesubject storage transaction (e.g., read 5 MBs of contiguous memory).Alternatively or additionally, a plurality of descriptors 130 may beused because the region of storage 104 that is the object of the storagetransaction is disposed in non-contiguous blocks. Descriptors 130 thatare associated with a single storage transaction may be designated byuse of the first bit field 140 and the last bit field 142. When adescriptor 130 is the first descriptor in a storage transaction, thefirst bit field 140 may be set to ‘1’ and the last bit field 142 may beset to ‘0.’ When a descriptor 130 is the last descriptor in a storagetransaction, the first bit field 140 may be set to ‘0’ and the last bitfield is set to ‘1.’ When a descriptor 130 is neither the first nor thelast descriptor in a storage transaction, both the first bit field 140and the last bit field may be set to ‘0.’

Turning now to FIG. 3A a plurality of source descriptors 150 associatedwith a data read transaction comprise a first source descriptor 152, asecond source descriptor 154, and a third source descriptor 156 for adata read transaction are described (e.g., a read of compressed datafrom storage 104, decompression of the data, and writing thedecompressed data to the memory 112). The first source descriptor 152,being the first source descriptor of a storage transaction, has itsfirst bit field set to ‘1’ and its last bit field set to ‘0.’ If thestorage transaction comprises only a single source descriptor, both thefirst bit field and the last bit field may be set to ‘1.’ The secondsource descriptor 154, being neither the first nor the last sourcedescriptor in the subject storage transaction, has both its first bitfield and its last bit field set to ‘0.’ There may be additionaldescriptors between the second and third source descriptors 154 and 156.The third source descriptor 156, being the last source descriptor in thesubject storage transaction, has its first bit field set to ‘0’ and itslast bit field set to ‘1.’ The first source descriptor 152 identifies afirst buffer 153 in storage 104, the second source descriptor 154identifies a second buffer 155 in storage 104, and the third sourcedescriptor 156 identifies a third buffer 157 in storage 104. Thelocations in storage 104 identified by the source descriptors 152-156represent the compressed data to be retrieved from storage 104 fordecompression and subsequent storage in memory 112. In an embodiment,only one source descriptor such as the first source descriptor in aplurality of source descriptors associated with a same transaction maycomprise the threshold field 138 while other source descriptorsassociated with the same transaction may omit the threshold field 138.

FIG. 3B illustrates a plurality of destination descriptors associatedwith the read data transaction. The destination descriptors in thisexample include a first destination descriptor 162, a second destinationdescriptor 164, and a third destination descriptor 166. The destinationdescriptors 162, 164, 166 need not specify the length or the command sothese fields may be omitted from the destination descriptors. The firstdestination descriptor 162, being the first destination descriptor of astorage transaction, has its first bit field set to ‘1’ and its last bitfield set to ‘0.’ If the storage transaction comprises only a singledestination descriptor, both the first bit field and the last bit fieldmay be set to ‘1.’ The second destination descriptor 164, being neitherthe first nor the last destination descriptor in the subject storagetransaction, may have both of its first bit field and last bit field setto ‘0.’ The third destination descriptor 166, being the last destinationdescriptor in the subject storage transaction, may have its first bitfield set to ‘0’ and its last bit field set to ‘1.’ The firstdestination descriptor 162 identifies a first buffer′ 163 in memory 112,the second destination descriptor 164 identifies a second buffer′ 165 inmemory 112, and the third destination descriptor 166 identifies a thirdbuffer′ 167 in memory 112 into which the decompressed data is to bewritten pending the data's return to the application 107 that requestedthe data.

The DMA engine 114 reads compressed data from storage 104 at locationsdesignated by source descriptors 152, 154, 156. The DMA engine 114streams the compressed data read from storage 104 to thecompression/decompression accelerator 116. The compression/decompressionaccelerator 116 decompresses the received compressed data and streamsthe decompressed data back to the DMA engine 114. The DMA engine writesthe received decompressed data into the memory 112 at locationsdesignated by the destination descriptors 162, 164, 166.

FIG. 4 illustrates an embodiment of the DMA engine 114. The DMA engine114 may comprise a DMA logic block 180. In some contexts, the DMA logicblock 180 may be referred to as a controller component. The DMA engine114 further may comprise one or more transaction blocks 182. Thetransaction block 182 may be a hardware component or an area in localmemory of the DMA engine 114, for example a block of local memory thatis dynamically allocated by the DMA logic block 180 to perform atransaction on the data storage 104. The transaction block 182 may storeinformation about a storage transaction, for example a plurality ofsource descriptors 184, a plurality of destination descriptors 186, atransaction identity 188, and a threshold 189. The transaction blockalso may be referred to as a control buffer. In a data write transaction(i.e., uncompressed data transmitted from the application 107 to becompressed and written to the storage 104) the transaction block 182 maynot employ or comprise a transaction identity 188 or a threshold 189.

The DMA logic block 180 may receive control inputs from the processor110 via control input 190, for example a storage transaction command,source descriptors 184, destination descriptors 186, and possibly othercontrol parameters such as a threshold or location value and/or anidentification of a compression algorithm or a decompression algorithmto be used in the storage transaction. In some embodiments, the DMAengine 114 couples to the memory 112 and the storage 114 via a singledata bus 192 and thus reads uncompressed data from and writesdecompressed data to the memory 112 on data bus 192 as well as writescompressed data to and reads compressed data from the data storage 104on the same data bus 192. In other embodiments, the DMA engine 114couples to the memory 112 and to the storage 104 via separate buses.That is, data bus 192 may represent a single bus or multiple buses. Insome contexts the data bus 192 may be referred to as a data interface ofthe DMA engine 114. The DMA logic block 180 may create and store atransaction identity for a data storage read transaction in thetransaction identity 188. The DMA logic block 180 provides read andwrite control in response to commands and parameters received on thecontrol input 190 as well as in response to the stop transaction signal122 and the second AXI stream 120. The control input 190 may be referredto in some contexts as a control interface, and the DMA logic block 180may be referred to in some contexts as a control circuit. The DMA logicblock 180 may be implemented as one or more of combinational logic,sequential logic a state machine, a microcontroller, or another logicstructure. Other architectures for the DMA engine 114 from that shown inFIG. 4 are possible as well.

Turning now to FIG. 5, an embodiment of the compression/decompressionaccelerator 116 is described. The compression/decompression accelerator116 may comprise a compression/decompression logic block 194 thatcomprises a count register 195, a threshold register 196, and atransaction identity register 197.

The compression/decompression accelerator 116 further may comprise aplurality of decompression algorithm processing blocks 198 embodied asprogram instructions (e.g., firmware) and a plurality of compressionalgorithm processing blocks 200 also embodied as program instructions.The compression/decompression logic block 194 may perform decompressionin accordance with a selected one of the processing blocks 198 andperform compression in accordance with a selected one of the compressionalgorithm processing blocks 200. Alternatively, the decompressionalgorithm processing blocks 198 and the compression algorithm processingblocks 200 may be implemented as logic components within the DMA logicblock 180. Alternatively, the decompression algorithm processing blocks198 may comprise a single decompression block that performs differentdecompression algorithms in response to having one or more decompressionblock configuration parameters set by the compression/decompressionlogic 194, and the compression algorithm processing blocks 200 maycomprise a single compression block that performs different compressionalgorithms in response to having one or more compression blockconfiguration parameters set by the compression/decompression logic 194.

The first AXI stream 118 may feed into the decompression algorithmblocks 198 and to the compression algorithm blocks 200. In anembodiment, the compression/decompression logic block 194 mayselectively enable communication from the first AXI stream 118 to one ofthe decompression algorithm processing blocks 198 or one of thecompression algorithm processing blocks 200, for example via controlline 199. This may be referred to as directing the first AXI stream 118to one of the decompression algorithm processing blocks or one of thecompression algorithm processing blocks 200. In an embodiment, thecompression/decompression accelerator 116 may comprise a multiplexer(not shown) that selects, under control of the compression/decompressionlogic block 194, which of the decompression algorithm processing blocks198 or which of the compression algorithm processing blocks 200 thefirst AXI stream 118 is coupled to.

The first AXI stream 118 may configure the compression/decompressionlogic block 194 for compression processing of uncompressed data streamsor for decompression processing of compressed data streams received onthe first AXI stream 118. The configuration commands may be sent fromthe DMA engine 114 to the compression/decompression accelerator 116 onthe first AXI stream 118 and may comprise an identification of which ofthe plurality of decompression algorithm processing blocks 198 or ofwhich of the plurality of compression algorithm processing blocks 200 toactivate. The configuration commands may further comprise a value tostore in the threshold register 196 and a transaction identity to storein the transaction identity register 197, depending on whether theapplication 107 requested a write or read transaction.

When the compression/decompression accelerator 116 is configured todecompress compressed data, the compression/decompression logic block194 increments the value stored in the count register 195 for each byteof compressed data that is decompressed by the selected decompressionalgorithm processing block 198 or for each unit of data of compresseddata that is decompressed by the selected decompression algorithmprocessing block 198. The unit of data may be something other than abyte of data. For example, the unit of data may be a minimum accessibleunit of data defined for the storage 104. The unit of data may be anumber of bytes corresponding to a row entry in a data base table (e.g.,the size of a single entry in a data base). The unit of data may bedetermined as some other amount of data. The compression/decompressionlogic block 194 streams decompressed data (or compressed data, ifreceiving a stream of uncompressed data to be compressed) to the DMAengine 114 via the second AXI stream 120. When the count 195 matches orexceeds the threshold 196, the compression/decompression logic block 194commands the selected decompression algorithm processing block 198 tostop processing compressed data received from the first AXI steam 118(or otherwise ceases data decompression) and sends a stop transactionsignal 122 to the DMA engine 114 along with the transaction identity197.

When the DMA engine 114 receives the stop transaction signal 122, itstops reading compressed data from the storage 104. In an embodiment, asthe DMA engine 114 reads buffers from storage 104 as indicated by thesource descriptors 150, the DMA engine marks source descriptors as“read” or “invalid” to indicate that the corresponding data has beenread. When the stop transaction signal 122 is received duringfulfillment of a request from the application 107 to read from storage104, the DMA engine 114 may mark unread source descriptors as “read” oras “invalid” so that the compressed data designed by such descriptors isnot read. The DMA engine may then conclude the read transaction with theprocessor 110, for example by asserting an end of transaction signal tothe processor 110.

Turning now to FIG. 6, a method 230 is described. In an embodiment, themethod 230 may be performed by the DMA engine 114 and thecompression/decompression accelerator 116 described above duringfulfillment of a data read request received from the application 107. Atblock 232, a direct memory access (DMA) engine coupled to a data storagereceives a plurality of source descriptors and destination descriptors,wherein the source descriptors identify a block of compressed datastored in the data storage and a threshold value that identifies alocation in a block of decompressed data derived from the block ofcompressed data. The destination descriptors identify locations inmemory 112 where corresponding decompressed data is to be stored. Atblock 234, the DMA engine reads the block of compressed data identifiedby the source descriptors from the data storage. At block 236, the DMAengine concatenates the block of compressed data read from the datastorage to form a compressed data stream.

At block 238, the DMA engine transmits the compressed data stream andthe threshold value to a decompression accelerator. The DMA engine mayfurther determine a transaction identity associated with the data readtransaction and send this transaction identity to the decompressionaccelerator. At block 239, the decompression accelerator decompressesthe compressed data stream to form a decompressed data stream whileincrementing a counter for each unit of decompressed data. At block 240,the decompression accelerator determines when the value of the countermatches or exceeds the threshold value. For example, the decompressionaccelerator may compare the value of the counter incremented in block239 to the threshold value sent by the DMA engine to the decompressionaccelerator in block 238. At block 242, when the counter is determinedto match or exceed the threshold value, the decompression acceleratorstops further decompression of the compressed data stream. Thedecompression accelerator may ignore further compressed data streamed toit from the DMA engine for a period of time, until the DMA engineinitiates a new decompression cycle, for example by sending a differentthreshold value and/or a different transaction identity. At block 244,in response to a determination that the counter matches or exceeds thethreshold value, the decompression accelerator transmits a stoptransaction signal to the DMA engine. In response to receiving the stoptransaction signal from the decompression accelerator, the DMA enginemay mark unprocessed source descriptors as invalid and may assert an endof transaction signal to the processor. After block 244 and in responseto receiving the stop transaction signal from the decompressionaccelerator, the DMA engine may discard all source descriptors of thecurrent transaction until and including a descriptor marked with a lastbit having a set value (e.g., having a ‘1’ value).

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, different companies may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In the following discussion and inthe claims, the terms “including” and “comprising” are used in anopen-ended fashion, and thus should be interpreted to mean “including,but not limited to . . . .” Also, the term “couple” or “couples” isintended to mean either an indirect or direct wired connection, wirelessconnection, or network connection. Thus, if a first device couples to asecond device, that connection may be through a direct connection orthrough an indirect connection via other devices and connections.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. A method of reading compressed data, comprising:receiving a plurality of source descriptors and destination descriptorsby a direct memory access (DMA) engine coupled to a data storage,wherein the source descriptors identify a block of compressed datastored in the data storage and a threshold value that identifies alocation in a block of decompressed data corresponding to the block ofcompressed data; reading the block of compressed data from the datastorage by the DMA engine; concatenating by the DMA engine the block ofcompressed data read from the data storage to form a compressed datastream; transmitting the compressed data stream and the threshold valueto a decompression accelerator by the DMA engine; decompressing thecompressed data stream to form a decompressed data stream by thedecompression accelerator while incrementing a counter for each unit ofdecompressed data; determining, by the decompression accelerator, whenthe value of the counter matches or exceeds the threshold value; whenthe counter is determined to match or exceed the threshold value,stopping further decompression of the compressed data stream by thedecompression accelerator; and transmitting a stop transaction signal tothe DMA engine by the decompression accelerator.
 2. The method of claim1, further comprising the decompression accelerator streaming thedecompressed data to the DMA engine and the DMA engine writing thedecompressed data to a memory.
 3. The method of claim 1, wherein the DMAengine determines a transaction identity to associate to the block ofcompressed data identified by the source descriptors and transmits thetransaction identity to the decompression accelerator.
 4. The method ofclaim 3, wherein the stop transaction signal transmitted by thedecompression accelerator comprises the transaction identity.
 5. Themethod of claim 1, wherein the location in the block of decompresseddata designates data that is to be read out of the compressed data. 6.The method of claim 1, wherein the unit of decompressed data is one of abyte or a record of a database.
 7. A direct memory access (DMA) circuit,comprising: a data interface configured to read data from and write datato a data storage coupled to the DMA circuit and configured to read datafrom and write data to a memory coupled to a processor and coupled tothe DMA circuit; a control interface configured to receive a pluralityof source descriptors and a plurality of destination descriptors fromthe processor, each source descriptor including a source locationaddress in the data storage, each destination descriptor including adestination location address in the memory, and at least one sourcedescriptor including a threshold value indicating a position in a streamof decompressed data; a control buffer into which the plurality ofdescriptors are stored; and a control circuit coupled to the datainterface, the control interface, and the control buffer, wherein thecontrol circuit is configured to: transmit the threshold value to adecompression accelerator; transmit compressed data to the decompressionaccelerator; receive decompressed data from the decompressionaccelerator; and upon receiving a stop transaction signal, stop readingthe compressed data from the data storage.
 8. The DMA circuit of claim7, wherein the stop transaction signal is received from thedecompression accelerator.
 9. The DMA circuit of claim 8, wherein one ofthe source descriptors comprises a transaction identity associated withthe plurality of source descriptors, wherein the control circuit isfurther configured to send the transaction identity to the decompressionaccelerators, and wherein the stop transaction signal comprises thetransaction identity.
 10. The DMA circuit of claim 8, wherein thecontrol circuit is further configured to determine a transactionidentity associated with the plurality of source descriptors and to sendthe transaction identity to the decompression accelerator.
 11. The DMAcircuit of claim 10, wherein each of the source descriptors comprises afirst bit and a last bit and wherein the control circuit is furtherconfigured to determine a new transaction identity that is incrementedfrom a previous transaction identity when a source descriptor having afirst bit active is received, whereby the start of a new data storageread transaction request is indicated.
 12. The DMA circuit of claim 10,wherein the stop transaction signal comprises the transaction identity.13. The DMA circuit of claim 12, wherein the control circuit is furtherconfigured to mark source descriptors associated with the transactionidentity received in the stop transaction signal as invalid.
 14. The DMAcircuit of claim 7, wherein the control circuit is further configured toread the compressed data from locations in the data storage identifiedby the plurality of source descriptors.
 15. An apparatus, comprising: adecompression accelerator comprising an electronic circuit including acounter and a decompression algorithm processing block, wherein thedecompression accelerator is configured to: receive a compressed datastream and a data count value threshold from a direct memory access(DMA) engine storing a source descriptor including the data count valuethreshold, the data count value threshold indicating a position in adecompressed data stream, decompress the compressed data stream by thedecompression algorithm processing block to produce the decompresseddata stream, increment a value stored in the counter for each unit ofdecompressed data, transmit the decompressed data stream, determine thatthe value stored in the counter matches or exceeds the data count valuethreshold, and stop decompressing the compressed data stream andtransmit a stop transaction signal.
 16. The apparatus of claim 15,further comprising a compression accelerator configured to receive anuncompressed data stream, to compress the uncompressed data stream, andto transmit the compressed data stream.
 17. The apparatus of claim 15,wherein the unit of decompressed data is a record of a database.
 18. Theapparatus of claim 15, wherein the unit of decompressed data is a byte.19. The apparatus of claim 15, wherein the decompression accelerator isfurther configured to receive a transaction identity, and wherein thestop transaction signal comprises the transaction identity.
 20. Theapparatus of claim 15, wherein the decompression accelerator comprises alogic block that directs the compressed data stream to the decompressionalgorithm processing block, reads the counter, and stops routing thecompressed data stream to the decompression processing block when thevalue read from the counter matches or exceeds the data count valuethreshold.